The present invention relates to a method for using magnetic memory, and more particularly, to a programming method for magnetic memory that reduces power consumption.
A resistance-based memory device normally comprises an array of memory cells, each of which includes a memory element and a selection element, such as transistor, coupled in series between two electrodes. The selection element functions like a switch to direct current or voltage through the selected memory element coupled thereto. Upon application of an appropriate voltage or current to the selected memory element, the resistance of the memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
FIG. 1 is a schematic circuit diagram of a memory array 20, which comprises a plurality of memory cells 22 with each of the memory cells 22 including an access transistor 24 coupled to a resistance-based memory element 26; a plurality of parallel word lines 28 with each being coupled to the gates of a respective row of the access transistors 24 in a first direction; a plurality of parallel bit lines 30 with each being coupled to a respective row of the memory elements 26 in a second direction substantially perpendicular to the first direction; and a plurality of parallel source lines 32 with each being coupled to a respective row of the access transistors 24 in the first or second direction.
Alternatively, the access transistors 24 of the memory cells 22 may be replaced by two-terminal bi-directional selectors to simplify the wiring scheme and allow stacking of multiple levels of memory arrays. FIG. 2 is a schematic circuit diagram of a memory array 40 incorporating therein two-terminal selectors as selection elements. The memory array 40 comprises a plurality of memory cells 42 with each of the memory cells 42 including a two-terminal bi-directional selector 44 coupled to a resistance-based memory element 46 in series; a plurality of first conductive lines 48A-48C with each being coupled to a respective row of the memory elements 46 in a first direction; and a plurality of second conductive lines 50A-50C with each being coupled to a respective row of the two-terminal selectors 44 in a second direction substantially perpendicular to the first direction. Accordingly, the memory cells 42 are located at the cross points between the first and second conductive lines 48A-48C and 50A-50C. The first and second conductive lines 48A-48C and 50A-50C may be bit lines and word lines, respectively, or vice versa. Multiple layers of the memory array 40 may be stacked on a wafer substrate to form a monolithic three-dimensional memory device.
The resistance-based memory elements 26 or 46 may be classified into at least one of several known groups based on their resistance switching mechanism. The memory element of Phase Change Random Access Memory (PCRAM) may comprise a phase change chalcogenide compound, which can switch between a resistive phase (amorphous or crystalline) and a conductive crystalline phase. The memory element of Conductive Bridging Random Access Memory (CBRAM) relies on the statistical bridging of metal rich precipitates therein for its switching mechanism. The memory element of CBRAM normally comprises a nominally insulating metal oxide material, which can switch to a lower electrical resistance state as the metal rich precipitates grow and link to form conductive paths or filaments upon application of an appropriate voltage. The memory element of Magnetic Random Access Memory (MRAM) normally includes a magnetic reference layer and a magnetic free layer with an electron tunnel junction layer interposed therebetween. The magnetic reference layer, the electron tunnel junction layer, and the magnetic free layer collectively form a magnetic tunneling junction (MTJ). When a switching current or voltage is applied to the MTJ, the magnetization direction of the magnetic free layer is switched with respect to the magnetization direction of the magnetic reference layer, thereby changing the electrical resistance of the MTJ.
Because of variations caused by the manufacturing process and the inherent stochastic switching behavior of MTJ, an array of magnetic memory cells may exhibit large variations in the actual programming time required to switch the resistance state. The wide distribution in programming time means that a small fraction of slower cells will required programming times that are several times longer than the rest of the cells. Therefore, the slower cells prolong the programming time for all cells in a conventional programming method that uses a fixed time period to program all cells, thereby adversely increasing power consumption.
For the foregoing reasons, there is a need for an efficient programming method that can reduce power consumption.